Current mode control also known as current programming regulating scheme is controlling method for switching mode power supply regulation. Specific of current mode control (CMC) is that this is a controlling method with two loops:
- Outer voltage loop
- Inner current loop
Schematically it is presented in the block diagram bellow.
The basic idea with CMC is to control inductor peak current in order to maintain output voltage constant. It is usually applied with constant frequency switch-on time. Since this is pulse width control (PWM) method, it is necessary to have analog comparator that will generate variable pulse width. In order to determine switch-off time, comparator compares two control signals:
- linear ramp
- PI or PID signal from the error regulator
For current mode control, linear ramp is actually inductor current sensed with sensing resistor or (that is more expensive) sensed with current sense transformer. Current mode control scheme applied on boost dc-dc converter is shown in figure bellow.
Active switch is turned “on” after every switching period. According to the scheme above, it will stay conductive as long as linear ramp (inductor current) is lower then the signal from error regulator (see figure bellow).
As soon as inductor current reaches error signal (ePI) comparator turns “off” active switch and active switch stays turned “off” until new switching pulse arrives. Such control approach has significant advantages. First, it has best (shortest) response time to any disturbance, comparing with all other control methods. If load and/or input voltage is suddenly changed, inductor current is also changed at time instant and this information is immediately transferred to control mechanism. This advantage come from inner current feedback. So current mode control has following good features:
- automatic over current (overload) protection
- fastest response time
- parallel operation of dc-dc converters is easy with current mode control
- it is applicable in push-pull dc-dc converter
However, current mode control has several disadvantages too. It is not practical if inductor current is too low (to small power consumption) or too high. For very small currents, current mode control is not immune to noises. If current is too high, power dissipation on sensing resistor is not acceptable. And, even if current is in optimal range, if duty cycle is higher then 50%, system will enter into bifurcation and instability. Mathematical reason for this instability was given by dr. Ridley. Physical explanation is given in figure bellow.
When average duty cycle is higher then 50%, slope up is smaller then slope down. Since ramp is starting to increase from previous position (does not start from zero, like voltage ramp in voltage mode control), if it is close to error signal ePI, during “off” time, current will not fall to the same position as in previous turn “on” time. Since current signal is now “higher”, it will “hit” ePI, is shorter time then in previous cycle. It means that now “off” time will last longer, and inductor current with slope down that is steeper then slope up will go lower then in previous two clock pulses. During next pulse, current might not even get to ePI, and this is how instability appeared. If compensation slope is subtracted from ePI signal, current mode is stabilized, but in that case, it has slower response.
In current mode control, error gain is higher if sensing resistor is smaller. Smaller sensing resistor multiplied with current will give smaller control ramp voltage. With smaller ramp, negative feedback will push ePI signal to lower value in order to maintain appropriate duty cycle. If sensing resistor is bigger, bigger will be control ramp voltage. In that case, negative feedback has to push ePI signal to higher value, and it takes time. Reason why compensation slope on ePI signal slows response time of current mode control is that ePI signal has to increase it’s height for the same amount that compensation slope has.
Read about voltage mode control and one cycle control.